Logic Design of NanoICS by Svetlana N. Yanushkevich, Vlad P. Shmerko, Sergey Edward

By Svetlana N. Yanushkevich, Vlad P. Shmerko, Sergey Edward Lyshevski

Common sense layout of NanoICs introduces a brand new concept-computer-aided good judgment circuit layout in nanometric house. this idea represents a leap forward from - to 3-dimensional puzzling over good judgment circuit layout and imparts a brand new knowing of knowledge processing on the atomic point. It provides a strong new method and ready-to-go algorithms for circuit layout and gives a suite of types and sensible ideas that might aid identify famous criteria and benchmarks for product trying out, tuning, and implementation. Designed for experts in nanoelectronics, this ebook also will function a great textbook that with path adoptions, deals a wealth of ancillary fabrics.

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There are two types of fault tolerance exhibited by a nanosystem: fault tolerance with respect to Data that is noisy, distorted or incomplete, which results from the manner in which data is organized and represented in the nanosystem, and The physical degradation of the nanosystem itself. © 2005 by CRC Press 16 Logic Design of NanoICs If certain nanodevices or parts of the network are destroyed, it will continue to function properly. When damage becomes extensive, it will only affect the system’s performance, as opposed to a complete failure.

The existing approach to design of digital nanoelectronic devices can be divided into two main streams corresponding to classification of single-electron interpretation of logic signals © 2005 by CRC Press Nanotechnologies 35 Voltage-state logic, and Charge-state logic. 1 Voltage-state logic: library of gates SET-based devices are based on voltage-state logic, originating from traditional silicon logic. 5 (see “Further Reading” Section). In voltage state mode, the input gate voltage controls the source-drain current of the transistor which is used in digital logic circuits, similarly to the usual FETs.

In design of high parallel systems and communication, a number of hypercube-like topologies have proved themselves to satisfy the above mentioned requirements of design methodology. However, the data structures that carry information about logic functions have a number of specific properties. This means that their © 2005 by CRC Press 10 Logic Design of NanoICs representation and manipulation are different from the same methods in high parallel systems and communication. 2 Representation of a switching function f = x1 x2 ∨ x1 x2 ∨ x1 x2 x3 by the classical hypercube (a) and N -hypercube (b) in three dimensions.

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